The present invention relates, in general, to integrated circuits and, more particularly, to field effect transistor memories.
Static memory cells typically have cross-coupled transistors combined with load devices to provide data storage. The memory cell includes pass-transistors controlled by a word line for either writing data to the memory cell for storage or reading the stored data for transfer to complementary bit lines.
The length of the complementary bit lines depends on the configuration of the memory array. Long complementary bit lines have large parasitic capacitance which slows the read operation from the memory cell. Because the transistors of the memory cells are small, they are unable to charge and discharge the parasitic capacitance of the complementary bit lines in a timely fashion.
Accordingly, a need exists for improving the speed of reading data stored in a memory cell. Further, it would be advantageous to improve the speed of the read operation without increasing the size of the memory cell.